MOUNTAIN VIEW, Calif.
Nov. 6, 2012
- Optimized memory test and repair algorithms efficiently address new memory defects, including process variation faults and resistive faults, at 20 nanometers (nm) and below
- New hierarchical architecture delivers up to 30 percent reduction in memory test and repair area
- Hierarchical implementation accelerates design cycles by allowing incremental generation, integration and verification of test and repair IP at various design hierarchy levels
- Support for test interfaces of high-performance processor cores enables designers to maximize productivity and system-on-chip (SoC) performance
Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced a new release of its DesignWare
STAR Memory System®
, an automated pre- and post-silicon memory test, debug, diagnostic and repair solution that enables designers to improve quality of results (QoR), reduce design time, lower test costs and optimize manufacturing yield. The latest release, targeting 20-nm- and FinFET-based designs, includes a new architecture enabling hierarchical implementation and validation of large SoC designs containing thousands of embedded memories, which can decrease the time required to implement tests while also reducing area by as much as 30 percent. In addition, the new release efficiently addresses test and repair for new memory defects seen in 20-nm processes and below such as process variation faults and resistive faults.
"With embedded memories occupying nearly 50 percent of an SoC, having a comprehensive memory test solution with built-in self-test and repair is critical to achieving optimal yield, while lowering overall costs," said
, IP Analyst at IPNest. "Synopsys' introduction of its next generation of the DesignWare STAR Memory System significantly improves designers' ability to detect specific memory defects and failure mechanisms that are prevalent in designs at 20 nanometers and below."
The new architecture in the STAR Memory System provides advanced memory addressing and programmable memory background patterns needed to create optimized test algorithms for detecting not only static and dynamic faults, but also process variation and resistive faults, which are more likely to occur at technology nodes of 20 nm and below. The new version also optimizes the test generation logic by storing only the unique test elements, providing significant area savings.