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Silicon Labs Introduces Low-Jitter Clock Buffers With Industry’s Highest Integration Of Clock Tree Functions

Silicon Laboratories Inc. (NASDAQ: SLAB), a leader in high-performance, analog-intensive, mixed-signal ICs, today introduced the industry’s first universal clock buffers capable of replacing LVPECL, LVDS, CML, HCSL and LVCMOS buffers with a single IC, eliminating the need for multiple fixed-format buffers. The new Si533xx family integrates common clock tree functions including clock distribution, clock muxing, clock division, format translation and level translation. Based on a patented low-phase-noise clock driver architecture, the Si533xx family features ultra-low additive jitter with guaranteed maximum jitter specifications, simplifying clock tree design and providing designers more jitter margin for other devices. The Si533xx clock buffers are purpose-built to address the demanding requirements of communications, data center, wireless infrastructure, broadcast video and embedded computing applications.

The Si533xx clock buffer family is part of Silicon Labs’ comprehensive portfolio of timing devices, enabling customers to simplify both the design and procurement of complete clock tree solutions for virtually any high-performance application. Silicon Labs-based clock trees provide the industry’s highest level of integration, minimizing the number of components necessary for clock generation and distribution. By being able to source all timing components from a single supplier, end-to-end performance can be guaranteed, eliminating interoperability headaches while simplifying the customer’s supply chain.

Competing clock buffers support only a single-output signal format and do not integrate basic clock tree functions. This deficiency forces system designers to use a variety of discrete buffers, muxes, dividers and level translators to address their clock distribution requirements, adding complexity and cost to their designs. Silicon Labs’ flexible and highly integrated solution resolves these issues, adding flexibility, simplifying clock trees, reducing design complexity and eliminating procurement headaches.

The Si533xx clock buffers provide a single-chip solution that replaces differential LVPECL, LVDS, CML and HCSL buffers with up to 10 outputs, LVCMOS buffers with up to 20 outputs, and discrete muxes, dividers and level translators. The unique architecture of the Si533xx clock buffers maximizes design flexibility. Clock outputs are split into two independent banks. The signal format of each bank is user-selectable through simple pin-strapping, providing developers with an array of options. Both banks have dedicated supply voltage pins independent of the core voltage, enabling simple voltage-level translation. The devices’ universal input stage accepts two differential or single-ended inputs, and a low-noise 2:1 input mux supports glitchless switching, eliminating the risk of runt pulses being transferred to the device outputs during an input clock switch. In addition, some Si533xx buffers support individual output enable pins for each output clock, providing control flexibility.

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