"We have been working closely with Synopsys for over a year to ensure seamless integration between Synplify and the Vivado Design Suite for customers using our 7 series FPGAs," said Tom Feist, senior marketing director of design methodology Xilinx. "In particular, the new constraints setup capability offered in the latest Synplify release has greatly helped our customers accelerate the creation of good design constraints and improve design performance."
Synopsys and Xilinx worked together to provide an integrated RTL-to-gates flow that simplifies the migration path to the Xilinx Vivado Design Suite for designers using Xilinx 7 Series FPGAs. The new flow adopts standard Synopsys Design Constraints (SDC) timing constraints specifications and provides the option to use the Verilog netlist format as the output from synthesis and input to place-and-route. The latest Synplify software also defines a migration path from Xilinx's ISE place-and-route flows to Vivado flows by providing constraints translation, constraints editing, review and reporting within the Synplify tool.
"Altera's FPGAs provide a proven solution for high-reliability applications," said Alex Grbic, director of software and IP marketing at Altera. "The enhanced TMR functionality in Synopsys' Synplify Premier software automatically implements the triplicated logic and associated voting and control mechanisms, providing a complementary solution to our Quartus II software. As a result of our longstanding partnership, customers using Altera devices can take advantage of the new high-reliability features in the Synplify Premier software for use in their mission-critical applications."
The Synplify Premier software's enhanced high-reliability features have been extended to support Altera devices, providing designers with the ability to create immunity to radiation effects that cause single event upsets (SEUs). In addition to enabling the creation of fault-tolerant sequential logic including state machines, the Synplify Premier software now allows designers to automatically implement error mitigation circuitry including automatically distributed TMR with voting logic, as well as perform automatic inference of Altera error correcting memory primitives.
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