"We have been working closely with Synopsys for over a year to ensure seamless integration between Synplify and the Vivado Design Suite for customers using our 7 series FPGAs," said Tom Feist, senior marketing director of design methodology Xilinx. "In particular, the new constraints setup capability offered in the latest Synplify release has greatly helped our customers accelerate the creation of good design constraints and improve design performance."Synopsys and Xilinx worked together to provide an integrated RTL-to-gates flow that simplifies the migration path to the Xilinx Vivado Design Suite for designers using Xilinx 7 Series FPGAs. The new flow adopts standard Synopsys Design Constraints (SDC) timing constraints specifications and provides the option to use the Verilog netlist format as the output from synthesis and input to place-and-route. The latest Synplify software also defines a migration path from Xilinx's ISE place-and-route flows to Vivado flows by providing constraints translation, constraints editing, review and reporting within the Synplify tool.
Latest Release Of Synplify Software Cuts Days Off FPGA Implementation Time
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