DALLAS, Oct. 29, 2012 /PRNewswire/ -- Texas Instruments Incorporated (TI) (NASDAQ: TXN) introduced a pair of devices today supporting the JEDEC JESD204B serial interface standard for data converters. The ADS42JB69 is the industry's first dual-channel, 16-bit analog-to-digital converter (ADC) featuring the JESD204B interface and is also the fastest at 250 MSPS. The LMK04828 is the industry's highest-performance clock jitter cleaner and is the first to support JESD204B clocking. When used together, the devices provide unmatched system-level performance for high-speed systems. For designs requiring a traditional parallel interface, the company also introduced the ADS42LB69, the industry's fastest dual, 16-bit ADC at 250 MSPS featuring an LVDS interface. For more information and to request samples, visit www.ti.com/jesd204b-pr.
JESD204B is an industry-standard serial communications link that simplifies the digital data interface between data converters and other devices, such as FPGAs, DSPs and ASICs. The standard reduces the routing between devices, slashing input/output and board space requirements for applications, such as wireless communications, test and measurement, and defense and aerospace.
The ADS42JB69 maximizes flexibility in system design, because it is the only 16-bit ADC incorporating all three JESD204B subclasses, 0, 1 and 2, allowing multi-device synchronization between data converters. The ADS42JB69 also supports the new JESD204B standard for deterministic latency, which provides fixed transmission delay with or without the use of an external timing signal. The device is also compatible with the existing JESD204A standard.Key features and benefits of the ADS42JB69 and ADS42LB69
- Highest dynamic performance to maximize receiver sensitivity: At 170 MHz intermediate frequency (IF), both ADCs provide spurious-free dynamic range (SFDR) performance of 89 dBc, up to 9-dB better than the competition, along with SFDR of 100 dBc, excluding harmonic distortion 2 (HD2) and HD3, signal-to-noise ratio (SNR) performance of up to 74.9 decibels relative to full scale (dBFS) and channel isolation of 100 dB.
- Maximum design flexibility with three digital interface choices:
- ADS42JB69 with JESD204B interface reduces the required number of data interface lanes from 17 to five, slashing board space while reducing design complexity.
- ADS42LB69 supports traditional parallel interface designs via 17 lanes of double data rate (DDR) low-voltage differential signaling (LVDS) or 10 lanes of quad data rate LVDS.
- Easy analog input interface: High-impedance analog input buffer with programmable full-scale range simplifies input filter design and drive circuitry. This also increases performance uniformity and device-to-device repeatability across the analog input frequency range.
- Lowest power consumption: The ADS42JB69 consumes 775 mW/channel, while the ADS42LB69 uses only 740 mW/channel.
- Pin-compatible family for design flexibility: The new ADCs are part of a family that includes pin-compatible, high-performance 14-bit options. The dual, 14-bit, 250-MSPS ADS42JB49 (JESD204B) and ADS42LB49 (LVDS) provide SFDR performance of 89 dBc and SNR performance of up to 73.4 dBFS at 170 MHz IF.
- Highest performance: Enables less than 100-fs RMS jitter (10 kHz to 20 MHz) at 245.76 MHz using a low-noise voltage-controlled crystal oscillator module.
- Unique combination of performance and functional integration: Reduces clock architecture complexity while providing options to maximize system performance and reduce component count and bill of material (BOM) costs.
- Generates JESD204B subclass 1 SYSREF: High-speed clocks are paired with JESD204B SYSREF companion signals to provide timing synchronization for up to seven subsystem JESD204B components.
- Greater flexibility:
- Dual voltage-controlled oscillator cores operating at 2.5 GHz or 2.9 GHz enable maximum flexibility by providing seven pairs of programmable clock outputs set as LVDS, low-voltage positive-emitter-coupled logic (LVPECL), or high-swing differential signaling (HSDS) output formats.
- Output pairs can be configured as a device clock and SYSREF, or as two device clocks for implementing additional high-speed clocks to meet system requirements.
- Programmable features, such as digital delay, analog delay and zero delay, support a variety of clocking requirements and architectures.
- 16-bit ADS42JB69SEK and 14-bit ADS42JB49SEK with JESD204B interface for US$999
- 16-bit ADS42LB69EVM and 14-bit ADS42LB49EVM with LVDS interface for US$399
- Request samples, purchase EVMs: http://www.ti.com/jesd204b-pr.
- Download the ADS42JB69 and ADS42JB49 data sheet: www.ti.com/ads42jb69-pr.
- Download the LMK04828 and LMK04826 data sheet: www.ti.com/lmk04828-pr.
- Download the ADS42LB69 and ADS42LB49 data sheet: www.ti.com/ads42lb69-pr.
- See how the ADCs and clock can benefit your system in this video: www.ti.com/jesd204bv-pr.