Traditional physical verification done after design closure is no longer adequate for complex designs, causing late-stage surprises and leading to an increasing number of time-consuming and error-prone design iterations. In-Design physical verification, based on intelligent integration between IC Validator and IC Compiler, makes it possible for place-and-route engineers to perform independent signoff-quality analysis earlier, before the design is finalized and while correction can be automated. In-Design technology enables new high-productivity functionality, such as automatic DRC repair, timing-aware metal fill and rapid ECO validation, all within the place-and-route environment. In-Design physical verification eliminates entire iterations with downstream analysis tools and maintains convergent design evolution to physical signoff.
"As manufacturing complexity places increased pressure on our customers to deliver within schedule, it is important that we continue to collaborate closely with leading foundries like UMC," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "This qualification brings the proven benefits of IC Validator and In-Design physical verification to UMC's customers working at advanced nodes."
About Synopsys Synopsys, Inc. (Nasdaq:SNPS) accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, its software, IP and services help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems. Learn more at http://www.synopsys.com.
Editorial Contacts: Sheryl Gulizia Synopsys, Inc. 650-584-8635 email@example.comLisa Gillette-Martin MCA, Inc. 650-968-8900 ext. 115 firstname.lastname@example.org SOURCE Synopsys, Inc.
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