Traditional physical verification done after design closure is no longer adequate for complex designs, causing late-stage surprises and leading to an increasing number of time-consuming and error-prone design iterations. In-Design physical verification, based on intelligent integration between IC Validator and IC Compiler, makes it possible for place-and-route engineers to perform independent signoff-quality analysis earlier, before the design is finalized and while correction can be automated. In-Design technology enables new high-productivity functionality, such as automatic DRC repair, timing-aware metal fill and rapid ECO validation, all within the place-and-route environment. In-Design physical verification eliminates entire iterations with downstream analysis tools and maintains convergent design evolution to physical signoff."As manufacturing complexity places increased pressure on our customers to deliver within schedule, it is important that we continue to collaborate closely with leading foundries like UMC," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "This qualification brings the proven benefits of IC Validator and In-Design physical verification to UMC's customers working at advanced nodes."
UMC Qualifies Synopsys' IC Validator For 28-nm Physical Verification
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