MOUNTAIN VIEW, Calif.
Oct. 22, 2012
- IC Validator brings In-Design physical verification to designers working at UMC's 28nm node
- In-Design physical verification eliminates late-stage design surprises and manual fixes
- Sign-off accurate Design Rule Checking (DRC) and layout-vs.-schematic (LVS) runsets now available for UMC customers
Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced that Synopsys' IC Validator physical verification product has been qualified by United Microelectronics Corporation for 28-nm physical signoff, with immediate availability of design rule checking (DRC) and layout-vs.-schematic (LVS) runsets to UMC customers. IC Validator, part of the Galaxy
Implementation Platform, is the ideal add-on to IC Compiler
for in-design physical verification, making it possible for place-and-route engineers to accelerate time to tapeout by eliminating late-stage surprises and manual fixes. IC Validator is being actively used at process nodes ranging from 65nm to 20nm. UMC's qualification of IC Validator brings the unique benefits of in-design physical verification to design teams working at UMC's 28-nm process node.
"UMC is committed to making available to its customers solutions that ensure silicon success while optimizing design turnaround time. As such, optimal runset creation and efficient maintenance are of paramount importance," said SC Chien, vice president of Customer Engineering& IP Development Design Support at UMC. "Runset creation with IC Validator was completed in record time for our 28-nanometer process node. In addition, our IC Compiler customers can now take advantage of the productivity benefits of In-Design physical verification for faster design closure."
As feature geometries shrink, the number and complexity of DRCs needed to achieve manufacturing compliance is growing exponentially. IC Validator makes runset creation and maintenance effortless for users by providing a hybrid engine for processing checks based on both polygon and edge data. Hybrid processing allows for efficient resolution of dependencies and more intelligent multi-core distribution, yielding faster runtimes. Furthermore, IC Validator enables coding at higher levels of abstraction, streamlining tedious lower-level data processing. Finally, IC Validator is architected for near-linear performance scalability that maximizes utilization of mainstream hardware, using smart, memory-aware load scheduling and balancing technologies.