(NASDAQ: MOSY), a leader in semiconductor solutions that enable fast, intelligent data access for network and communications systems, today announced a new second-generation Bandwidth Engine® IC optimized for advanced random access performance of 100G, 200G and 400G networking applications. The device is based on a dual-ported, single-bank, partitioned architecture that substantially cuts random access cycle time, enabling a dramatic increase in the processing rate capability of networking equipment. The
Bandwidth Engine family of ICs
is designed and built for high reliability, carrier-grade applications.
The new device, MSR720, will extend Bandwidth Engine capabilities through the ability to simultaneously read and write to a specific memory location. The unique device architecture maintains full data coherency, high command efficiency and simplified scheduling, resulting in a performance of up to 4.5 Giga-Accesses per second (GA/s). The high access rates and reduced effective cycle time of the MSR720 access device are well suited to the requirements of state memory and queuing applications, where repeat access of the same address is needed.
Using 16 SerDes lanes at 15 Gigabits per second (Gbps), the MSR720 interface operates at 480 Gbps, providing the host with up to 270 Gbps CRC protected, effective data throughput. The device also supports 36-bit half-word write capabilities which improve the command bus utilization. The culmination of these features improves performance beyond the capability of standard memory subsystems, while occupying less board area, using fewer interface pins, and consuming less power.
Network system access rate requirements far exceed the access rate at which traditional solutions can enable real-time access to packet header data. The second generation Bandwidth Engine architecture will close this performance gap for customers with its MSR720 device architecture and will deliver on these requirements, resulting in the highest performance single chip networking memory solution available today.
“Our second generation Bandwidth Engine architecture will support purpose-built variants to optimize specific applications and access types," stated
John Monson, Vice President of Marketing for MoSys
. "The addition of true random access functionality and faster effective cycle time in the MSR720 will deliver leading-edge performance in high data rate, low latency networking applications such as state memory, queuing and scheduling.”
MoSys’ Bandwidth Engine family of ICs utilizes the
, an open, 90 percent efficient, reliable transport protocol optimized for chip-to-chip communications. The device is compatible with CEI-11G and XFI SerDes which allows a seamless interface with high performance FPGAs, as well as standard libraries available from ASIC providers. A complete package of RTL and tools is available to support the Bandwidth Engine interface.
MoSys' first generation Bandwidth Engine IC has been fully qualified for carrier-grade applications and is available for volume production now. For information about Bandwidth Engine pricing and availability, contact a local MoSys sales representative at
This press release may contain "forward-looking statements" about MoSys, including, without limitation, expected benefits of the Bandwidth Engine ICs, product development of Bandwidth Engine ICs, the capabilities and adoption of the GigaChip Interface, and anticipated benefits and performance results expected from the use of MoSys' ICs.