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Analog Devices Simplifies High-Speed Data Converter-to-FPGA Interconnect Design Environment (Graphic: Business Wire)

Communications infrastructure, imaging equipment, industrial instrumentation, defense electronics and other multi-channel, data-hungry systems are demanding wider resolutions and higher sampling rates from the data conversion stage. Physical layout constraints of the parallel interface and bit-rate limitations of the serial LVDS (low-voltage differential signaling) approach are beginning to present technical barriers for designers.

To address this need, Analog Devices, Inc. (ADI:NASDAQ), a global leader in high-performance semiconductors for signal-processing applications and the leading provider of data-conversion technology*, today introduced the AD9250 dual-channel, 14-bit, 250 MSPS, A/D converter featuring the JEDEC JESD204B serial output data interface standard. The AD9250 A/D converter is the first-to-market with full JESD204B Subclass 1 deterministic latency at 250 MSPS. This functionality accommodates the precise synchronization of multiple data-conversion channels through a serial interface.

The AD9250 A/D converter’s serial interface implementation provides up to 5 Gbps over a 1 or 2 lane-capable link. Two serial lanes are used to support the full 250-MSPS, dual-A/D converter data rate, or a single lane can be used to support reduced sampling rates.

High-performance FPGA suppliers, such as Xilinx Inc., have incorporated on-chip JESD204B SerDes (serializer/deserializer) ports into their latest generation products. This end-to-end seamless connectivity for the analog signal chain results in simplified PCB layout, rapid prototyping capability, and faster time-to-market.

“Xilinx is fully-committed to supporting the JEDEC JESD204B standard and is striving to accelerate adoption of the serialized interconnect technology for data converters. We are doing this by providing a high quality flexible, scalable and programmable IP to interface with high speed data converters like the AD9250,” said Sunil Kar, Senior Director Wireless Business Group at Xilinx. “Xilinx currently provides JEDEC JESD204B IP for subclass 0, 1 and 2 functionality with line rates up to 10.3 Gb/s and lane widths ranging from x1 to x8 on our devices. This combination of technology advancements improves system modularization, lowers cost and complexity and will enhance the capabilities and capacities of next generation wireless and wired networks.”

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