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EZchip Introduces NPS, A New Breed Of C-Programmable NPU That Enables The Next Wave Of High-Performance Smart Carrier And Data-Center Networks

"We are bringing to market a new breed of network processor that is architected to address the next generation of smart high-performance carrier and data-center networks. Leveraging the 10-years of experience with our NP family that made EZchip the leading high-speed NPU supplier, we believe the NPS will extend and broaden our leadership for many years to come. We are preserving NPU performance advantages, opening the L4-7 markets for us and doubling EZchip's addressable market above and beyond serving edge routers," said Eli Fruchter, President and CEO of EZchip Technologies. "As for our main market of edge routers, NPS extends our competitive advantage and leapfrogs the competition. Combined with our future NP products, NPS can potentially increase our market penetration in next generation edge routing by providing current and new customers with the flexibility to adopt existing or new architectures, for basic and advanced line cards."

"We applaud EZchip for its bold move in developing the NPS, which truly redefines the network processor by stripping away traditional limitations," said Bob Wheeler, senior analyst at The Linley Group. "Only the market leader could develop such a ground-breaking product as the NPS while preserving its customers' software investments by also extending the NP line."

The NPS is a new product line of NPUs from EZchip. Initially, EZchip will deliver the NPS-400 and NPS-200 products with 400-Gigabit and 200-Gigabit throughput, respectively. Samples are planned for Q4 2013 and other derivative products will follow. EZchip customers for the NP-2/3/4/5 products will have the option to maintain the benefits of code portability and scale up with a future NP-6, or C-program their applications and benefit from the new capabilities of the NPS.

The NPS provides great packet processing simplicity and flexibility through C-based programming, a standard toolset, support of the Linux ® operating system, large code space, and a run-to-completion or pipeline programming style. A comprehensive library provides source code for a variety of applications to speed customer's design cycle. The NPS features cores that are highly optimized for packet processing and leverage EZchip's vast packet processing and applications experience, a market-proven traffic manager, hardware accelerators for security and DPI (Deep Packet Inspection) tailored for efficiency and performance, on-chip search engines including TCAM with scaling through algorithmic extension to external low-cost low-power DRAM memory, a fabric adaptor to enable direct connection to a chassis backplane and switch fabric, and a multitude of interfaces providing an aggregated bandwidth of 800-Gigabits per second including 10-, 40- and 100-Gigabit Ethernet, Interlaken and PCI Express interfaces.

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