YOKNEAM, Israel, September 5, 2012 /PRNewswire/ --
NPS is a new product line of NPUs that uniquely features a combination of unmatched:
- Technology - 10 times smaller and faster C-programmable Task Optimized Processors (CTOPs)
- Integration - NPU with 256 CTOPs, 4K threads, Traffic Manager, DPI, Security, Search Engine and 800G I/O in one chip
- Performance - 400-Gigabit wire-speed packet processing
- Flexibility - advanced services and full layers 2-7 stateful processing
- Simplicity - easy to use C-programmable and Linux ® operating system
- Versatility - addressing carrier, cloud and data-center networking equipment
- Applications - switching, routing, SDN/OpenFlow and virtualization of network elements, load balancing, TCP offload, firewall, VPNs, intrusion detection/prevention, network analytics and more
EZchip Semiconductor Ltd. (NASDAQ:EZCH), a leader in Ethernet network processors, today unveiled the NPS - Network Processor for Smart networks - a revolutionary network processor (NPU) that will enable the next generation of smart high-performance carrier and data-center equipment. Through its breakthrough architecture the NPS boosts the flexibility and performance of traditional NPUs and CPUs to enable advanced baseline features for carrier equipment and to scale the performance levels of data-center equipment. NPS provides equipment vendors with a feature-proof, fully programmable, high performance solution and expands the market addressable by EZchip's NPUs. EZchip will present details of the NPS architecture at the Linley Tech Processor Conference on October 10-11, 2012 in San Jose, California.With the continuous surge of subscribers, content and applications on the net, carrier and data-center networks are under constant pressure to operate faster and do more. This demand for network bandwidth and intelligence produces an insatiable appetite for processing power in networking equipment. Network-equipment vendors essentially have had a choice of two types of processors: NPUs that provide fast layer 2-3 processing however with complex microcode programming, and CPUs (single or multi-core) that provide flexible C-programmable layer 4-7 processing however at reduced performance and power efficiency. Through its breakthrough architecture, NPS breaks the barriers imposed by traditional NPUs and CPUs. It enables extremely high-performance C-programmable layer 2-7 processing, and provides networking vendors with an architecture that scales as more advanced services at higher speeds are required over time.
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