STMicroelectronics fuse our encounter digital and virtual custom analog platforms to complete a 20 nanometer mix signal test chip. Our Encounter and virtual platforms received Phase I certification for TSMC 20 nanometer technology. We collaborated with Samsung on the 20 nanometer methodology that includes double patterning technology. The number of 20 nanometer engagement with key customers is growing in every region, overall we are working with 16 different customers at 20 nanometer with more than 30 designs in progress or complete using encounter. At 40 nanometer process note we had joint projects underway and are working on test chips. The increased complexity of modern SoC is driving demand for our advanced verification solutions.In Q2, we closed a significant order for our incisive verification platform with a top 10 semi-conductor company. I have some exciting progress to report in the physical verification area. As a result on going collaboration TSMC is now making DRC and LDS Root/x (ph) available for our physical verification system product at a 28 and 20 nanometer nodes. This is yet another proof point that our investment at 20 nanometer node is producing competitive products and creating new opportunities for us.
Cadence Design Systems CEO Discusses Q2 2012 Results - Earnings Call Transcript
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