MOUNTAIN VIEW, Calif. and SHANGHAI, July 10, 2012 /PRNewswire-Asia/ --
- Latest collaboration yields availability of 15 Synopsys® DesignWare® IP products on SMIC's 40-nanometer low-leakage (40LL) process technology, enabling designers to incorporate functionality more easily into advanced low-power SoCs
- Proven interface PHY IP, including PCI Express®, USB and DDR, helps SoC designers ensure interoperability with the latest standards
- High-quality analog IP, including audio codecs and data converters, helps designers meet low-power, application-specific SoC requirements
- Embedded memories and logic libraries for the SMIC 40LL process enable design teams to optimize entire SoC designs for both speed and energy efficiency
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, and Semiconductor Manufacturing International Corporation ("SMIC"; NYSE: SMI; SEHK: 981), China's largest and most advanced semiconductor foundry, today announced the availability of a broad set of Synopsys DesignWare IP on the SMIC 40-nanometer (nm) low-leakage (40LL) process. The SMIC 40LL process technology combines advanced immersion lithography, strain engineering, ultra shallow junction and ultra low-k dielectric to deliver the optimized power and performance required of mobile multimedia and consumer devices. By offering a wide range of proven IP on SMIC's advanced low-power process, Synopsys is enabling designers to incorporate more functionality into their advanced system-on-chip (SoC) designs with less risk and faster time to market. Since 2005, the collaboration between Synopsys and SMIC has resulted in Synopsys' delivery of a broad portfolio of IP supporting SMIC processes from 130-nm to 40-nm.
Synopsys DesignWare IP available now or scheduled to be available later this year on the SMIC 40LL process includes:
- Interface IP for widely used protocols such as USB 2.0/3.0, PCI Express 2.0/1.1, MIPI, SATA, DDR, and HDMI that reduces interoperability risk
- Audio codec and data converter IP, optimized for a wide range of high-performance, low-power applications
- Embedded memories and logic libraries that enable designers to achieve both high speed and low power across the entire SoC
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