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Synopsys And SMIC Announce DesignWare IP For 40-nm Low-Leakage Process

MOUNTAIN VIEW, Calif. and SHANGHAI, July 10, 2012 /PRNewswire-Asia/ --

  • Latest collaboration yields availability of 15 Synopsys® DesignWare® IP products on SMIC's 40-nanometer low-leakage (40LL) process technology, enabling designers to incorporate functionality more easily into advanced low-power SoCs
  • Proven interface PHY IP, including PCI Express®, USB and DDR, helps SoC designers ensure interoperability with the latest standards
  • High-quality analog IP, including audio codecs and data converters, helps designers meet low-power, application-specific SoC requirements
  • Embedded memories and logic libraries for the SMIC 40LL process enable design teams to optimize entire SoC designs for both speed and energy efficiency

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, and Semiconductor Manufacturing International Corporation ("SMIC"; NYSE: SMI; SEHK: 981), China's largest and most advanced semiconductor foundry, today announced the availability of a broad set of Synopsys DesignWare IP on the SMIC 40-nanometer (nm) low-leakage (40LL) process. The SMIC 40LL process technology combines advanced immersion lithography, strain engineering, ultra shallow junction and ultra low-k dielectric to deliver the optimized power and performance required of mobile multimedia and consumer devices. By offering a wide range of proven IP on SMIC's advanced low-power process, Synopsys is enabling designers to incorporate more functionality into their advanced system-on-chip (SoC) designs with less risk and faster time to market. Since 2005, the collaboration between Synopsys and SMIC has resulted in Synopsys' delivery of a broad portfolio of IP supporting SMIC processes from 130-nm to 40-nm.

Synopsys DesignWare IP available now or scheduled to be available later this year on the SMIC 40LL process includes:
  • Interface IP for widely used protocols such as USB 2.0/3.0, PCI Express 2.0/1.1, MIPI, SATA, DDR, and HDMI that reduces interoperability risk
  • Audio codec and data converter IP, optimized for a wide range of high-performance, low-power applications
  • Embedded memories and logic libraries that enable designers to achieve both high speed and low power across the entire SoC

"Access to a broad portfolio of silicon-proven IP in a high-performance, low-power process technology is critical for companies designing SoCs for multimedia consumer products in China and around the world," said Chris Chi, Chief Business Officer at SMIC. "Our collaboration with Synopsys offers designers targeting the consumer market a proven path to a wide range of technology-leading IP on advanced process nodes. Our first-pass silicon success with Synopsys' DesignWare USB, HDMI and audio codec IP, where all critical performance metrics meet or exceed the target specifications, demonstrates the stability and maturity of SMIC's 40LL technology."

"Our longstanding collaboration with SMIC provides SoC designers with optimized IP across a range of processes for widely used interface protocols such as USB, PCI Express and DDR, as well as foundational elements such as logic libraries and embedded memories," said John Koeter, vice president of marketing for IP and systems at Synopsys. "Together, we have a track record of silicon success over a range of IP from 130-nm to 65-nm. Extending our IP offerings to SMIC's 40LL process allows designers to take advantage of SMIC's advanced low-leakage process technology and integrate high-quality IP with less risk."


DesignWare USB 2.0 picoPHY, HDMI 1.4 TX PHY, DDR multiPHY, MIPI D-PHY, PCI Express 2.0/1.1 PHY, SATA 1.5Gb/s/3Gb/s PHY, SATA 6Gb/s PHY, and select audio codecs and data converter IP are available now from Synopsys on the SMIC 40LL process. DesignWare USB 3.0 PHY, HSIC PHY, data converters and AFE for LTE and Wi-Fi, and Embedded Memory and Logic Library IP are available for early adopters. Availability for the DesignWare HDMI RX PHY and DDR3/2 PHY IP is planned for Q4 2012.

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