Xilinx Unveils The Vivado Design Suite For The Next Decade Of 'All Programmable' Devices

SAN JOSE, Calif., April 24, 2012 /PRNewswire/ -- Xilinx, Inc. (NASDAQ: XLNX) today announced the Vivado™ Design Suite, a new IP and system-centric design environment built from the ground up to accelerate design productivity for the next decade of 'All Programmable' Devices. Vivado tools not only speed the design of programmable logic and I/O, but accelerate programmable systems integration and implementation into devices incorporating 3D stacked silicon interconnect technology, ARM® processing systems, Analog Mixed Signal (AMS), and a significant percentage of semiconductor intellectual property (IP) cores. With up to a 4X productivity advantage over competing development environments, the Vivado Design Suite attacks the major bottlenecks in programmable systems integration and implementation.

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"Vivado tools are the culmination of work started by Xilinx engineers in 2008 in response to customers' needs for more productivity, faster time to market, and the ability to go beyond programmable logic to programmable systems integration. It has been beta tested with more than 100 customers and Alliance Program members over the past 12 months, including customers using our stacked silicon interconnect-based Virtex®-7 devices for extreme capacity and bandwidth," said Xilinx senior vice president of platforms development, Victor Peng.

Vivado Design Environment The Vivado Design Suite provides a highly integrated design environment (IDE) with a completely new generation of system-to-IC level tools, all built on the backbone of a shared scalable data model and a common debug environment. It is also an open environment based on industry standards such as the AMBA4 AXI4 interconnect specification, IP-XACT IP packaging metadata, the Tool Command Language (Tcl), Synopsys Design Constraints (SDC) and others that facilitate design flows tailored to the user's needs. Xilinx architected Vivado tools to enable the combination of all types of programmable technologies and scale up to 100-million-ASIC equivalent gate designs.

To address integration bottlenecks, the Vivado IDE includes electronic system level (ESL) design tools for rapidly synthesizing and verifying C-based algorithmic IP; standards based packaging of both algorithmic and RTL IP for reuse; standards based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems with 3X faster simulation, while hardware co-simulation provides 100X more performance.

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