ARM today announced the availability of a high performance, power-optimized quad-core hard macro implementation of its flagship Cortex™-A15 MPCore™ processor.
The ARM® Cortex-A15 MP4 hard macro is designed to run at 2GHz and delivers performance in excess of 20,000DMIPS, while maintaining the power efficiency of the Cortex-A9 hard macro. The Cortex-A15 hard macro development is the result of the unique synergy arising from the combination of ARM Cortex processor IP, Artisan® physical IP, CoreLink™ systems IP and ARM integration capabilities, and utilizes the TSMC 28HPM process.
The low leakage implementation, featuring integrated NEON™ SIMD technology and floating point (VFP), delivers an extremely competitive balance of performance and power and is ideal for wide array of high-performance computing applications for such as notebooks through to power-efficient, extreme performance-orientated network and enterprise devices.
The hard macro was developed using ARM Artisan 12-track libraries and the recently announced Processor Optimization Pack™ (POP) solution for the Cortex-A15 on TSMC 28nm HPM process. This follows the recent announcement of a broad suite of POPs for all Cortex-A series processors (see
ARM Expands Processor Optimization Pack Solutions for TSMC 40nm and 28nm Process Variants
Full configuration and implementation details will be presented at the Cool Chips conference (18-20 April) in Yokohama, Japan. Further information is contained in an accompanying
“For SoC designers looking to make a trade-off between the flexibility offered by the traditional RTL-based SoC development strategy and a rapid time to market, with ensured, benchmarked power, performance and area, an ARM hard macro implementation is an ideal, cost-effective solution,” said Jim Nicholas, vice president of marketing, processor division, ARM. “This new Cortex-A15 hard macro is an important addition to our portfolio and will enable a wider array of partners to leverage the outstanding capabilities of the Cortex-A15 processor.”