Xilinx Announces Industry's First Dual 100 Gbps Gearbox Solution For Interfacing CFP2 Optical Modules To Virtex-7 HT FPGAs

SAN JOSE, Calif., March 5, 2012 /PRNewswire/ -- Xilinx, Inc. (NASDAQ: XLNX) today announced the industry's first dual 100 Gbps Gearbox solution for connecting 100G interfaces with the newest generation of high-density, 100 Gbps CFP2 optical modules. Incorporating a single 28nm Virtex®-7 HT FPGA and Xilinx Gearbox intellectual property (IP) cores, the solution overcomes the initial hurdles of leveraging the new CFP2 optics supporting 100GE, OTU4 and 10x 10 MSA specifications. This allows higher density 100G line cards and transmission equipment while lowering overall system power consumption and solution cost through integration. By offering the implementation based on the Virtex-7 HT FPGA family with 28 Gbps transceivers, Xilinx can provide communications customers with twice the density and more advanced debugging features compared to competing devices as well as replace what would be a three chip ASSP design.

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The global demand fueled by the surge in multimedia content and the rise of cloud computing is creating an unquenchable thirst for more bandwidth. This in turn is driving the need for adoption of more high-speed 100G interfaces with higher port densities in the optical and packet networking equipment across the network – core, aggregation, data center and transmission. The move toward increased numbers of 100G interfaces per line card in the core and aggregation nodes has become critical to achieve scale, network simplicity and an overall cost reduction in running and managing networks. CFP2 optical modules that are half the size of CFP modules with significantly lower power consumption require an external 100G gearbox to achieve density gains and power advantages based on their form factor. Further gains are achieved when both the CFP2 modules and the gearbox conform to 100GE, OTU4 and 10x 10 MSA specifications, which require using 4x 25G and 10x 10G serial links schemes for systems side interfaces. A single IP core for connecting multiple 100G interfaces into a single chip takes integration to the next level. Combining the Xilinx Dual 100G Gearbox with other OTN or packet processing functionality in a single chip provides an unprecedented level of integration, while reducing overall systems power and lowering the total BOM costs by up to forty percent.

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