MOUNTAIN VIEW, Calif, Feb. 9, 2012 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced that CSR plc, a leader in wireless, location and audiovisual technology, has deployed Synopsys' Galaxy™ Implementation Platform for the design of its 40-nanometer (nm) system-on-chips (SoCs). CSR cited the Galaxy platform's ability to deliver a robust hierarchical SoC design flow while converging on aggressive timing, area, and power goals as a key advantage of collaborating with Synopsys. CSR design teams are globally distributed, with key SoC groups in Cambridge, UK; Haifa, Israel; Shanghai, China and Phoenix, Arizona. Synopsys' highly responsive global support and expert consultants in efficient flows for ARM® CPU-based design were instrumental in CSR's decision to select Synopsys.
"We maintain our leadership in digital cameras, automotive navigation processors and other consumer markets by delivering innovative SoCs to our customers on time," said Babak Bastani, vice president of global chip design at CSR. "By using the silicon-proven Galaxy Platform, we are able to predictably tape out differentiated designs that deliver superior performance with low power consumption, which is critical to our success in these mobile computing markets."
CSR successfully adopted the Galaxy platform for its 40-nm, high-end Coach14 digital camera chip. This very complex SoC has millions of instances and intellectual property (IP) blocks, including Synopsys' DesignWare® USB 2.0 and DDR IP. Because logic synthesis, physical implementation and signoff are all tightly integrated in the Galaxy platform, CSR was able to deploy a hierarchical flow from synthesis to place-and-route to signoff and achieve on-time tapeout while meeting all of its design specifications.
Key components of the Galaxy platform include:
- Design Compiler® Graphical with IC Compiler: Provides faster RTL-to-physical convergence from initial design exploration through concurrent multi-corner/multi-mode (MCMM) optimization, and closure for timing, power, testability and area;
- IC Compiler Zroute technology: Offers concurrent design-for-manufacturability (DFM) routing for advanced process technologies. Coupled with In-Design physical verification via IC Validator, IC Compiler enables fast multicore, lithography-aware routing and delivers full compliance with complex DRC rules required for advanced silicon nodes; and
- PrimeTime® HyperScale technology: Speeds block-level timing closure in the context of the top-level design, dramatically accelerating signoff of complex, hierarchical designs.
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