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ISSI Expands QUAD And DDR-II Families Of SRAMs

Stocks in this article: ISSI

SAN JOSE, Calif., Feb. 15, 2011 (GLOBE NEWSWIRE) -- Integrated Silicon Solution, Inc. (Nasdaq:ISSI), a leader in advanced memory solutions, today introduced the latest additions to its QUAD and DDR-II families of SRAMs. These devices are based on 65nm technology and have speeds up to 500MHz.

These new families comprise 36Mb QUAD, 36Mb QUADP, 36Mb DDR-II and 36Mb DDR-IIP devices. Burst of 2 and Burst of 4 is supported and package options include leaded and lead free BGA. The devices are offered in x18 and x36 configurations and come in commercial and industrial temperature ranges.

The new QUADP and DDR-IIP products feature On-Die Termination (ODT). ODT improves signal integrity, reduces system cost, and saves board space by eliminating external termination resistors.  Latency options for QUADP and DDRIIP products include 2.0 and 2.5 clock cycles.

These devices are ideal for communications applications such as core and edge routers, Ethernet switches, and base stations. Other target applications include industrial test equipment, medical imaging and military systems.

The addition of these new SRAMs strengthens ISSI's portfolio of SRAM products, which includes 72Mb QUAD and DDR-II SRAMs, a synchronous portfolio ranging from 2Mb to 36Mb densities and one of the industry's broadest offerings of asynchronous SRAMs.

Samples will be available in April, with production quantities in July 2011.

"Along with our recent announcement of RLDRAM® 3 memory, this new 36Mb QUADP and DDR-IIP introduction exemplifies the steps that ISSI is taking to become a leader in high speed memory solutions for the communications market," said Pat Lasserre, Director of Strategic Marketing for the Telecom and Networking Segment. "Our strategy of long-term support aligns well with the communication market, which requires 10+ years of support".

QUAD SRAM is a type of memory that can transfer up to four words of data each clock cycle. QUAD SRAM transfers data on both rising and falling edges of the clock signal. The main purpose of this capability is to enable reads and writes to occur at high clock frequencies. QUADP SRAM is a higher-speed version of QUAD SRAM and DDR-IIP SRAM is a higher speed version of DDR-II SRAM.

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